RISC's Early History, or RISCtory

I'm a fan of Motorola's 68000 series CPU architecture. It has a lot of features and is designed to be an ideal target for compiled C and PASCAL code, but also has many core instructions that are written as plain English (like MOVE and ADD) which make it simple enough to write directly in assembly. It was very popular and used in a lot of high end computer systems... then RISC showed up and kicked it in the crotch.

EDUCATION

YOURSELF

Episode 000


Part 1: Of Course They Did

Once upon a time in the early 1980s, the US military wanted complete and total superiority in computing technology. In doing so, they pulled up a paper by a college professor by the name of Andrew S. Tanenbaum, a guy who would more famously go on to goad some kid into making a hobby kernel that totally won't become big. In this paper, he examined the compiled code from many different companies, and found that only a small subset of the available instructions and addressing modes of the target CPU were actually in use. Therefore, he proposed that it would be possible to create a CPU that [i]only[/i] worked on this subset of functionality, and that said CPU could be hyper-optimized to perform operations much more efficiently.

Now, IBM was working on making such a CPU a reality, but were having more failures than success. The military didn't know about this, so they instead wanted to do it themselves... or rather, have someone do it for them. Using their public-facing R&D arm, DARPA, they went to the best source for cheap, talented minds that can pull it off: college students! So they went to the University of California, Berkeley, and (one year later) their next-door neighbor Stanford University, to challenge them to make it happen in exchange for sweet, sweet government money.

Part 2: Making it Happen

Both teams at Berkeley and Stanford independently encountered and solved similar problems while creating their solutions. The first big issue was memory. Now, those older "CISC" processor designs did have one advantage over the new concepts, which is the density of the code. CISC designs can do multiple smaller operations with a single instruction, which uses up a lot less memory to store. The new designs can outpace it, but this was accomplished by bypassing the "microcode" aspect of CISC designs, which maps those operations to an instruction. In doing so, the needed code to do an equivalent operation increased, which meant you needed more memory, which was rather expensive back then. However, through clever use of a fixed-length instruction coding scheme, along with intelligent instruction usage, this issue was able to be sidestepped.

The second big issue was, what to do with all the reads and writes to memory? Memory is the slowest part of the system, and needing to read in and write out values took a lot of time. However, the actual processing part of their CPU designs was really small, because they no longer needed a huge footprint for the microcode's mask ROM and decoder. So they took the free real estate and turned it into the most valuable resource on a processor: registers! With lots and lots of registers, reading and writing memory could be done less frequently, speeding up overall processing.

Each team did something a bit different in this regard. Berkeley's project, called RISC, opted to have loads and loads of registers with a movable "window" for accessing them. This way, when going into a subroutine, rather than need to spend time dumping the current registers into the stack in memory, the register window can just be slid down to the next set of registers for a clean workspace, then slid back up when it was time to exit the subroutine. Very efficient! Of course, if you go too deep, you run out of register space and are forced to use the stack instead. Meanwhile, Stanford's project, MIPS, just gave a wall of registers and made proper usage the programmers' problem. This made programming a bit trickier, but made the resulting CPU die much smaller.

Part 3: Berkeley Takes a RISC

Berkeley RISC was finally unveiled in 1981, and went into a test production run. However, the production was full of problems and mishaps, and mask designs had to be scrapped four different times. Finally in May of 1982, Berkeley RISC had actual chips for real world testing. And it was in this testing that... they found more problems that kneecapped the overall speed and stability of the design. Nevertheless, they pitted their 4MHz RISC I CPU against the VAX 11/780 and Zilog Z8000, both of which were clocked at a faster 5MHz, and absolutely curbstomped them. Despite the lower clock speed and the design flaws, the RISC I was twice as fast as the VAX and four times as fast as the Z8000! Not only that, but the fabrication process used was a much older one, so if they could have used the same process that was used to make, say, the 68020, then the performance uplift would be even greater.

While all of this was going on, a second group was working on an improvement, the RISC II. Despite being slowed down by RISC I's production and student graduation, the RISC II design managed to simplify several aspects of the original considerably, at the cost of making memory timings a lot tighter. However, they also managed to increase the size of the register space while also reducing the transistor count. In 1983, actual silicon was produced, and it managed to be even faster than the RISC I against the VAX! Compared to the venerable 68000 from the introduction, it outperformed it by 420%. (lol weed number)

Part 4: MIPS Is Too Shy

Unfortunately, very little is written about what went on with MIPS. This seems to coincide with the fact that, as soon as Stanford finished the project in 1984, the team responsible immediately started a company for it, called MIPS Computer Systems. They then made a revision to the ISA and produced commercial MIPS, starting with the R2000 CPU. Perhaps the lack of information is because the team wanted to keep it all as trade secrets? This is unfortunate, as this reduces the information available to the general public to "yeah it happened". But, why would the Stanford MIPS team want to rush to make their design into a commercial product?

Part 5: Here Comes The Sun

Sun Microsystems made UNIX workstations using 68000-family CPUs. They heard about the Neat Shit that was going on at Berkeley, and decided to check it out. Berkeley was playing around with RISC II, creating experimental offshoots like SOAR (aka RISC III) which ran Smalltalk directly on the CPU, and SPUR (aka RISC IV) which was the basis for a multiprocessor Lisp workstation. Sun really liked the idea, and took home the RISC II design. They worked it over, and in 1986, they created SPARC. In 1987, they put it into their UNIX workstations, and steamrolled the competition. This created a massive race to get or develop RISC designs, just to stay competitive. DEC started making the Alpha processor, HP started work on PA-RISC, and SGI just vores MIPS Computer Systems. IBM even figured out the problems with their experiments and actually creates the 801, followed by a new design that would become the POWER architecture. Some bigger names struggled in this time to make their own RISC designs, namely Motorola's 88000 and Fairchild's Clipper, which didn't really go anywhere.

But Sun was not the only one to use Berkeley RISC as a basis for a new architecture. Intel and AMD both went to the same proverbial well for their RISC designs, with Intel's i860 and later i960 leading up to a dumpster fire, and AMD's Am29000 leading up to the AMD K5. Sophie Wilson, a lass from the UK, also took the design with her back to The Europes to her place of work, Acorn Computers, and created the Acorn RISC Machine, which now powers every single smartphone on the market.

Oh, and the US military and the competiton they set up? The winner was obvious: it was MIPS. They replaced all their home-grown CPU designs with MIPS.

NEXT TIME ON EDUCATION YOURSELF

Better address that dumpster fire... who wants to make smores?